System-on-chip including DRAM &amp; analog device for improving DRAM capacitance and method for fabricating the same

ABSTRACT

Provided is an invention related to a SOC containing a DRAM and an analog device for increasing a capacitance of a capacitor in SOC and a method of fabricating the SOC. Two conductive layers are used for lower electrode in a capacitor for unit cells of the DRAM, and the whole surface of the upper electrode is capped with a second dielectric layer to maximally increase in the contact surface between the dielectric layer and the upper and lower electrodes.

BACKGROUND OF THE INVENTION

This application claims the priority of Korean Patent Application No.2003-60766 filed on Sep. 1, 2003, in the Korean Intellectual PropertyOffice, the disclosure of which is incorporated herein in its entiretyby reference.

1. Field of Invention.

The present invention relates to an integrated semiconductor device anda method of fabricating the same, and more particularly, to asystem-on-chip containing a DRAM and an analog device, and a method offabricating such a system-on-chip.

2. Background of the invention.

Advances in semiconductor manufacturing techniques have lead to aconsiderable reduction in the size of electronic products. This has madepossible the development of products called “systems on chip” (SOC)products. SOCs are chips that perform multiple functions. SOCs have beendeveloped for products in various fields. Moreover, a new SOC containinga DRAM and an analog device has been introduced.

An SOC containing a DRAM and an analog device generally includes acapacitor used as a unit cell for a DRAM. The capacitor should have asurface that is large enough to ensure a high capacitance. However, dueto the requirement of high integration, it is necessary to form acapacitor having a high capacitance in a narrow space. Decreasing thesize of the capacitor allows a reduction in the size of the analogdevice, thereby increasing the overall degree of integration.

Several attempts have been made to increase the density of capacitors inSOCs containing a DRAM and an analog device. In general, there are threemethods of increasing the capacitance of a semiconductor capacitor basedon the fact that, in general, the capacitance of a semiconductorcapacitor is directly proportional to the surface of electrode and thedielectric constant of the dielectric layer, and inversely proportionalto the thickness of the dielectric layer.

The first method involves increasing the contact surface between theelectrode and the dielectric layer of the capacitor. That is, thecapacitance is increased by designing an upper electrode and a lowerelectrode of the capacitor in a three-dimensional configuration.However, this method has a drawback in that making the capacitor in athree-dimensional configuration requires a relatively complicatedmanufacturing process.

The second method involves making a capacitor with a thin dielectriclayer. Since the capacitance is inversely proportional to the thicknessof the dielectric layer, the capacitance can be increased by decreasingthe thickness of the dielectric layer. However, there is a limit howmuch the thickness of the dielectric layer can be decreased owing to thecharacteristic of the dielectric layer itself.

The third method involves adopting a material with a high dielectricconstant for the dielectric layer. However, this method also has manydisadvantages. For example it may be difficult to adapt a new dielectricmaterial to an existing process. Furthermore it may require a newelectrode material and to it is necessary to verify the reliability ofthe new electrode material.

SUMMARY OF THE INVENTION

The present invention provides a SOC containing a DRAM and an analogdevice having a high capacitance capacitor in a DRAM. The presentinvention also provides a method of fabricating a SOC containing a DRAMand an analog device for increasing the capacitance of the capacitor inthe DRAM.

In accordance with an aspect of the present invention, an SOC containinga DRAM and an analog device includes a capacitor which has a lowerelectrode separated from an upper electrode by a dielectric layer. Theupper electrode is patterned containing holes or indentations and it iscovered by a second dielectric layer. The second dielectric layer is inturned covered by an upper conductive layer that is connected to thelower electrode. Thus the lower electrode and the upper conductive layertogether form the electrode of a high capacitance capacitor.

In accordance with another an aspect of the present invention, the SOCcomprises, a substrate, a lower part containing a DRAM and an analogdevice circuitry formed on the substrate, a first interlayer insulatinglayer formed on the lower part, a first conductive layer formed on thefirst interlayer insulating layer performing as a lower electrode of theDRAM, a first dielectric insulating layer formed on the first conductivelayer and, a second conductive layer pattern formed on the firstdielectric insulating layer. The second conductive layer serves as anupper electrode of the DRAM. The second conductive layer is shielded andcovered by the second dielectric insulating layer. The second dielectriclayer is covered by a third conductive layer. The upper electrode,second dielectric layer, and the third conductive layer are patternedwith holes or indentations to increase the capacitance. The thirdconductive layer fills and covers the second dielectric layer pattern,and it performs as another electrode of the DRAM. A second interlayerinsulating layer covers the surface of the substrate where the thirdconductive layer is located. A metal pattern for an upper electrode islocated on the second interlayer insulating layer and it connects to theupper electrode through a first contact plug. A second metal pattern onthe second interlayer insulating layer connects to the lower electrodethrough a second contact plug.

In accordance with another aspect of the present invention, there isprovided a method of fabricating a SOC containing a DRAM and analogdevice such as that described above.

According to the present invention, the contact surface between thedielectric layer and the upper and lower electrodes can be extended atmaximum by using two conductive layers as the lower electrode and bycapping the surface of the upper electrode with the second dielectriclayer, thereby increasing the density of capacitance of the capacitorfor SOC containing a DRAM and analog device.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1 through 6 are cross-sectional views of a SOC which will be usedto describe a method of fabrication of an SOC containing a DRAM and ananalog device in accordance with the present invention.

FIG. 7 is a perspective view of a SOC for describing a formation of thesecond conductive layer pattern for the SOC containing a DRAM and ananalog device.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, the present invention will be described more fully withreference to the accompanying drawings. However, this invention may beembodied in many different forms and should not be construed as beinglimited to the embodiments set forth herein. Rather, theses embodimentsare provided so that the disclosure is thorough and complete and fullyconveys the concept of the invention to those skilled in the art.

An embodiment of an SOC containing a DRAM and an analog device inaccordance with the present invention as it is being formed is shown inFIGS. 1 to 6. The device at various stages in the manufacture thereof isshown in FIGS. 1 to 5. The completed device is shown in FIG. 6. As shownin FIG. 6, the SOC is formed on a semiconductor substrate 100. The SCOhas a lower part 102 that contains a DRAM and an analog device exceptfor the capacitors. The lower part 102 contains conventional circuitrythat what will be herein referred to as DRAM circuitry.

On top of layer 102 there is a first insulating layer 104. A firstconductive layer 106 is located on top of insulating layer 104. Layer106 forms a lower electrode for the DRAM. On top of lay 106 there is adielectric layer 108A. There is a second conductive layer pattern 110Aformed on the dielectric layer 108A. Layer 110A is an upper electrodefor the DRAM. Layer 110A has a pattern of holes or indentations 113 asshown in FIG. 7. As will be explained the holes or indentations are usedto increase the capacitance of the capacitor. Layer 110A is shielded orcovered by a second dielectric layer 112A. A third conductive layer 114forms another lower electrode of the DRAM. Layer 114 fills and coversthe pattern of holes or indentations in the second conductive layerpattern 110A. An etch stopper layer 116 covers he third conductive layer114.

The SOC also includes a second insulating layer 120 on the whole surfaceof the semiconductor substrate on top of the etch stopper layer 116. Ametal pattern 126 which forms an upper electrode is located on top ofthe second insulating layer 120. Electrode 126 connects through a firstcontact plug 122 located in the second insulating layer 120. A metalpattern 124 forms the lower electrode, and electrode 124 connectsthrough a contact plugs 118A and 118B located in the second insulatinglayer 120.

Among the main features of the present invention are first, the use ofthe two separate conductive layers to form the lower electrodes, i.e.,the first conductive layer 106 and the third conductive layer 114. Thesecond is capping of the second conductive layer 110A with a seconddielectric layer 112A. Layer 112A forms another dielectric layer of thecapacitor and functions with dielectric layer 108A. The surface area ofthe electrode is increased because the second conductive layer pattern110A which forms the upper electrode is covered on all surfaces. Thatis, the upper, lower and side surfaces of layer 110A are in contact withthe dielectric layers 108A and layer 112A. Accordingly, the capacitancedensity can be increased.

Here in after, a method of fabricating a SOC containing a DRAM and ananalog device according to the present invention will be described indetail with reference to the accompanying FIGS. 1 and 7.

Referring to FIG. 1, a lower part 102 includes conventional circuitryincluding in this specific embodiment a DRAM and an analog device(except capacitors). Lower part 102 is formed on a semiconductorsubstrate 100 in accordance with a conventional method. Layer 102 ishereinafter referred to as DRAM circuitry. Afterward, a first interlayerinsulating layer 104 is formed on the lower part 102, and the layer isplanarized.

A first conductive layer 106 which will be used as a lower electrode ofthe DRAM is formed on the first interlayer insulating layer 104. Thefirst conductive layer 106 is formed of a material selected from thegroup consisting of aluminum, polysilicon doped with impurities, andsilicide. Also, the first conductive layer 106 can further includetitanium nitride as a barrier layer to avoid the interface reaction witha dielectric layer 108 which will be formed in following process. Thefirst conductive layer 106 is preferably connected to the lower part 102through a contact plug, not shown in the drawing.

Next, a first dielectric insulating layer 108 is formed, as thin aspossible, on the first conductive layer 106. The first dielectric layer108 can be formed of a single layer selected from the group consistingof silicon oxide (SiO2), silicon nitride (SiN), oxide silicon nitride(SiON), aluminum oxide (AiO), and tantalum oxide (TaO), or a compositelayer containing at least one of the above insulating layers. That is,the material of the first dielectric layer 108 can be a material whichcan be formed in a thin layer, and which has a high dielectric constant.

Next, a second conductive layer 110 which will perform as an upperelectrode of the DRAM is formed on the dielectric insulating layer 108.The second conductive layer can be formed of a layer selected from thegroup consisting of aluminum, polysilicon doped with impurities, andsilicide. Also, the second conductive layer 110 can further includetitanium nitride (TiN) as a barrier layer to avoid the interfacereaction with the dielectric layer 108. Increasing the thicker thesecond conductive layer 110 increases the capacitance.

As shown in FIG. 2, layers 108 and 110 are patterned. After depositing aphoto-resist (not shown) on the whole surface of the second conductivelayer 110, a conductive layer pattern 110A and a dielectric layerpattern 108A are formed by a conventional method of photolithographicand etching processes.

Referring to FIG. 3, a second dielectric insulating layer 112A in auniform thickness is formed on the resultant structure. Accordingly,layer pattern 110 is capped with the second dielectric layer 112. Theresult is a pattern that increases the capacitance.

The configuration of the second conductive layer pattern 110 and thepattern unit 113 (FIG. 7, 113) will be described referring to the FIG.7. The configuration of the pattern unit (FIG. 7, 113) can be formed inany shape as long as it can increase the surface area of the secondconductive layer pattern 110. Preferably, the shape can be a square, arectangle, a circle, or a composite shape of these shapes. That is, inthe present invention, the surface of the pattern unit (FIG. 7, 113) canbe increased by forming it in a square shape as depicted in the drawing,thereby increasing the capacitance as much as the surface of the square.

The second dielectric layer 112 forms another dielectric layer of thecapacitor in the DRAM together with the first insulating layer pattern108A. The second dielectric insulating layer 112 also can be formed of asingle layer selected from the group consisting of silicon oxide (SiO2),silicon nitride (SiN), oxide silicon nitride (SiON), aluminum oxide(AiO), and tantalum oxide (TaO), or a composite layer containing atleast one of the above insulating layers. Also, for the improvement ofthe capacitance of a capacitor as the object of the present invention,the material of the second dielectric layer 112 can be replaced by amaterial which can be formed in a thin layer, and has a high dielectricconstant.

Referring to FIG. 4, a third conductive layer 114, which will perform asanother lower electrode of the DRAM, is formed on the entire of thesubstrate where the second dielectric layer 112A is located. It isnecessary to pattern the third conductive layer 114 to expose a portionof the second conductive layer pattern 110A to the outside. This is, toform a contact between the conductive layer pattern 110A and the metalpattern 126. The third conductive layer 114 can be formed of the samematerial as the first and the second conductive layers 106 and 110.

Referring to FIG. 5, an etch stopper layer 116 is formed on the entiresurface of the substrate where the third conductive layer 114 is formed.The etch stopper layer has an etch selectivity with the secondinterlayer insulating layer 120 and it can be formed of a layer selectedfrom the group consisting of silicon nitride, oxidized silicon nitride,and silicon oxide. The reason for forming the etch stopper layer 116 isto avoid problems of over etching or incomplete through hole of thecontact holes for forming the first and second contact plugs 122, 118A,and 118B when forming metal patterns for an upper electrode 126 in FIG.6 and a lower electrode 124.

Referring to FIG. 6, a second interlayer insulating layer 120 is formedon the substrate where the etch stopper layer 116 is formed. The secondinterlayer insulating layer 120 is formed for reducing step coveragewhen forming the capacitor. It can be formed of a single layer or acomposite layer of silicon oxide. Next, the contact holes for electricalconnection of metal patterns for upper and lower electrodes are formedthrough the second interlayer insulating layer 120 by photolithographicand etching processes. Then the first contact plug 122 and the secondcontact plugs 118A and 118B are formed by filling the contact holes witha conductive material such as tungsten or aluminum. One of the secondcontact plugs 118A is connected to the third conductive layer 114 andthe other is connected to the first conductive layer 106.

Next, the metal pattern 126 for upper electrode, connecting to the firstcontact plug 122, and the metal pattern 124 for lower electrodeconnecting to the second contact plugs 118A and 118B are formed of aconductive material like aluminum. The process for forming the metalpattern 126 for upper electrode and the metal pattern 124 for lowerelectrode in the second interlayer insulating layer 120 can be conductedby the so called damascene process using copper instead of aluminum.

For a capacitor according to the present invention, the contact surfacebetween the dielectric layers and the upper and lower electrodes can beextended at maximum by using two conductive layers as the lowerelectrode and by capping the surface of the upper electrode with thesecond dielectric layer. Accordingly, the capacitance density of acapacitor for SOC containing a DRAM and analog device can be increased.

It is noted that the capacitors formed in layers 104 to 114 areconnected to the conventional circuitry in layer 102 by conventionalconnections (not specifically shown in the drawings) as needed.

Also, in accordance with an embodiment of the present invention, thesecond interlayer insulating layer can comprise an etch stopper layerthere under, and the etch stopper layer is a layer having an etch madeof a material selectivity with the second interlayer insulating layer,and preferably can be formed of a layer selected from the groupconsisting of silicon nitride, oxidized silicon nitride, and siliconoxide.

In accordance with an aspect of the present invention, there is provideda method of fabricating a SOC containing a DRAM and analog devicecomprising forming a lower part on a semiconductor substrate includingthe DRAM and an analog device, sequentially depositing a firstinterlayer insulating layer, a first conductive layer performing as alower electrode of the DRAM, and a first insulating layer performing asa dielectric layer of the DRAM on the lower part, forming a secondconductive layer performing as an upper electrode of the DRAM on thefirst insulating layer, forming a second conductive layer pattern bypatterning the second conductive layer and the first insulating layer,forming a second insulating layer on the whole surface of the substrateafter patterning the second conductive pattern, forming and patterning athird conductive layer performing as another lower electrode of the DRAMon the semiconductor substrate where the second insulating layer isformed, forming a second interlayer insulating layer for covering stepof the semiconductor substrate where the third conductive layer ispatterned, forming a metal pattern for upper electrode connecting to thesecond conductive layer pattern and a meal pattern for lower electrodeconnecting to the first and the third conductive layer on the secondinterlayer insulating layer.

According to the preferred embodiment of the present invention, a methodof fabricating the SOC containing a DRAM and analog device furthercomprises forming an etch stopper layer after forming and patterning thethird conductive layer pattern.

Preferably, the third conductive layer is patterned to expose a portionof the second conductive layer pattern to the outside. According to apreferred embodiment of the present invention, the first and secondinsulating layers preferably can be formed of a single layer made of ametal selected from the group consisting of silicon oxide (SiO), siliconnitride (SiN), oxidized silicon nitride (SiON), aluminum oxide (AlO),and tantalum oxide (TaO), or a composite layer including at least one ofthe above insulating layers, and the first through the third conductivelayers preferably can be formed of a conductive layer selected from thegroup consisting of aluminum, polysilicon, and silicide.

The first through the third conductive layers can further comprise abarrier layer like titanium nitride (TiN).

The pattern unit of the second conductive layer pattern can be square,rectangle, circle, or a combination of these for increasing the contactsurface between the second and third conductive layers and the seconddielectric layer. The term hole as used herein means hole orindentation.

While this invention has been particularly shown and described withreference to a preferred embodiment thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the sprit and scope of the inventionas defined by the appended claims.

1. A SOC containing a DRAM and an analog device, comprising: asubstrate; a lower part on said substrate containing circuitry; ainterlayer insulating layer on top of said lower part; a firstconductive layer on said first insulating layer, said first conductivelayer forming a lower electrode for said DRAM; a first dielectric layerfor said DRAM formed on said first conductive layer; a second conductivelayer on said dielectric layer and forming an upper electrode of saidDRAM, said second conductive layer having a pattern of holes therein; asecond dielectric layer filling and covering the second conductive layerpattern, a third conductive layer filling and covering the seconddielectric layer, and performing as another lower electrode of the DRAM;a second interlayer insulating layer formed for covering the wholesurface of the substrate where the third conductive layer is formed; ametal pattern for upper electrode formed on the second interlayerinsulating layer connecting to the upper electrode through a firstcontact plug which is formed in the second interlayer insulating layer;and a metal pattern for lower electrode formed on the second interlayerinsulating layer connecting to the lower electrode through a secondcontact plug.
 2. The SOC containing a DRAM and an analog device of claim1, wherein the first and the second interlayer insulating layers areformed of a material selected from a group consisting of silicon oxide(SiO2), silicon nitride (SiN), oxide silicon nitride (SiON), aluminumoxide (AlO), and tantalum oxide (TaO).
 3. The SOC containing a DRAM andan analog device of claim 1, wherein the first and the second insulatinglayers are formed of a composite layer selected from an insulating layergroup consisting of silicon oxide (SiO2), silicon nitride (SiN), oxidesilicon nitride (SiON), aluminum oxide (AlO), and tantalum oxide (TaO).4. The SOC containing a DRAM and an analog device of claim 1, whereinthe first through the third conductive layers are formed of a layerselected from a conductive layer group consisting of aluminum,polysilicon, and silicide.
 5. The SOC containing a DRAM and an analogdevice of claim 4, wherein the first through the third conductive layersfurther comprise a barrier layer.
 6. The SOC containing a DRAM and ananalog device of claim 5, wherein the barrier layer is formed oftitanium nitride (TiN).
 7. The SOC containing a DRAM and an analogdevice of claim 1, wherein the pattern unit of the second conductivelayer pattern is shaped to increase the contact surface between thesecond and third conductive layers and the second dielectric layer. 8.The SOC containing a DRAM and an analog device of claim 7, wherein theshape for increasing the contact surface between the second and thirdconductive layers and the second dielectric layer is a square, arectangular, a circle or a composite shape of these shapes.
 9. The SOCcontaining a DRAM and an analog device of claim 1, wherein the firstcontact plug is formed for electrical connecting the second conductivelayer pattern to the metal pattern for upper electrode.
 10. The SOCcontaining a DRAM and an analog device of claim 1, wherein the secondcontact plug is formed for electrical connecting the first and thirdconductive layers to the metal pattern for lower electrode.
 11. The SOCcontaining a DRAM and an analog device of claim 1, wherein the secondinterlayer insulating layer further comprises an etch stopper layerthereunder.
 12. The SOC containing a DRAM and an analog device of claim1, wherein the second interlayer insulating layer is formed of a layerselected from a single layer or a composite layer of silicon oxide. 13.The SOC containing a DRAM and an analog device of claim 11, wherein theetch stopper layer is a layer having an etch selectivity with the secondinterlayer insulating layer
 14. The SOC containing a DRAM and an analogdevice of claim 13, wherein the etch stopper layer is formed of a layerselected from a group consisting of silicon nitride, oxidized siliconnitride, and silicon oxide.
 15. A method of fabricating a SOC containinga DRAM and an analog device, comprising: forming a lower part includingthe DRAM and the analog device circuitry on a substrate; depositingsequentially on said lower part, a first interlayer insulating layer, afirst conductive layer forming a lower electrode of the DRAM, and afirst dielectric layer; forming a second conductive layer on said firstdielectric layer, said second conductive layer forming an upperelectrode of said DRAM; patterning said second conductive layer and saidfirst dielectric layer; forming a second dielectric layer on the surfaceof the substrate after patterning the second conductive layer; formingand patterning a third conductive layer on the substrate where thesecond dielectric layer is formed, said third conductive layerperforming as another lower electrode of said DRAM; forming a secondinterlayer insulating layer where the third conductive layer ispatterned; forming a metal pattern for upper electrode connecting to thesecond conductive layer pattern and a metal pattern for lower electrodeconnecting to the first and third conductive layers on the secondinterlayer insulating layer.
 16. The method of claim 15, furthercomprising a step of forming an etch stopper layer on the substrateafter forming and patterning the third conductive layer pattern.
 17. Themethod of claim 16, wherein the etch stopper layer is a layer having anetch selectivity with the second interlayer insulating layer.
 18. Themethod of claim 17, wherein the etch stopper layer having an etchselectivity with the second interlayer insulating layer is formed of alayer selected from a group consisting of silicon oxide, siliconnitride, and oxide silicon nitride.
 19. The method of claim 15, whereinthe third conductive layer is patterned to expose a portion of thesecond conductive layer pattern to outside.
 20. The method of claim 15,wherein the second interlayer insulating layer is formed of a layerselected from a single layer of silicon oxide, and a composite layer ofsilicon oxide.
 21. A capacitor for a DRAM comprising: a first conductivelayer said first conductive layer forming a lower electrode for saidDRAM; a first dielectric layer for said DRAM formed on said firstconductive layer; a second conductive layer on said dielectric layer andforming an upper electrode of said DRAM, said second conductive layerhaving a pattern with holes therein; a second dielectric layer fillingand covering the second conductive layer pattern including the inside ofsaid holes holes, a third conductive layer filling and covering thesecond dielectric layer pattern of holes including the inside of saidholes, and forming another lower electrode of said DRAM; a connectionbetween said first and third dielectric layers.